Senior Functional Verification Engineer (Memory Subsystem)
Core
Lead verification for high-speed memory interfaces (UCIe, DDR5/6, HBM) using simulation and formal methods to ensure functional correctness of memory controller designs.
Role type
Senior IC verification engineer (memory subsystem)
Builds
Memory controller IPs and SoC designs for high-performance computing and AI applications
Domain
Semiconductor / VLSI / High-speed memory interfaces
Required skills
UVM/OVM, System Verilog, Verilog, simulation environments (VCS, IES), memory controller protocols, skew/jitter modeling, technical leadership, verification strategy, assertion-based verification, regression management, formal property checking, gate-level simulation, silicon debug
Preferred skills
UCIe verification, verification architecture, verification methodology design, formal tools (Jasper, Synopsys), power verification, reset verification, contention checking
Technologies
UVM, OVM, System Verilog, Verilog, Synopsys VCS, Cadence IES, Jasper, Cadence, Synopsys
Responsibilities
Design and develop simulation/formal verification environments at block and SoC level, drive verification strategies for high-performance IPs, lead teams of 9+ engineers, influence design teams to improve product quality, manage verification closure and delivery
Seniority
Senior, hands-on IC with leadership
