Senior Manager - Analog Design
Core
Manage the Memory I/O design team to define, specify, simulate, and implement future LPDDR IPs, focusing on high-speed analog and digital circuit architecture, calibration algorithms, and link performance models.
Role type
Senior Manager, Analog Design (Memory I/O)
Builds
LPDDR PHYs and high-speed data path components for AMD processors
Domain
Semiconductor / High-Speed Analog & Digital Design
Required skills
Circuit architecture design, High-speed analog/digital block design, Calibration and equalization algorithms, Link performance modeling, Team management, Risk mitigation, System integration (signal/power integrity), RTL/Firmware debugging
Preferred skills
Leading multiple PHY designs to silicon, Circuit-architecture and modeling for High Speed IOs, Hands-on knowledge of equalization/calibration/clocking, PHY modeling tools (Matlab/Simulink, Verilog/AMS), IO and system integration, Team management leading IPs to production
Technologies
LPDDR, PHY, Matlab, Simulink, Verilog, AMS
Responsibilities
Define circuit architecture and design low power/area-efficient circuits for LPDDR PHYs, Collaborate with Analog Mixed Signal, Digital Design, Firmware, and Verification teams, Manage execution and deliverables across customers and stakeholders, Develop models for link-level statistical performance simulation, Document micro-architecture and algorithms, Define development flows to improve efficiency and quality
Seniority
Senior, hands-on IC with management responsibilities
