IO / Analog Design Engineer – High Speed Memory Interfaces (m/f/d)
Core
Design new architecture, analysis, and validation of high-speed memory IO interfaces, combining hands-on circuit understanding with system-level thinking.
Role type
Senior IC analog/mixed-signal design architect
Builds
High-speed memory interface architectures and PHY concepts for next-generation memory technologies
Domain
Semiconductor / Memory / High-speed digital interfaces
Required skills
Mixed-signal IO block design, Schematic design, Circuit simulation (SPICE), Schematic entry (Cadence/Synopsys), Block-level modeling, Unix/Linux environments
Preferred skills
Scripting (Python/TCL/SKILL/Perl), Extraction and modeling tools, Cross-functional collaboration in semiconductor environment
Technologies
Cadence, Synopsys, SPICE, Unix/Linux
Responsibilities
Define and own IO and PHY concepts for high-speed memory interfaces, Perform block-level simulation, analysis, and feasibility checks, Review and guide schematic-level implementation, Support verification, silicon bring-up, and debug activities, Collaborate with global cross-functional teams, Use AI automation tools to improve modeling and analysis workflows
Seniority
Senior, hands-on IC
