Senior RTL Design Engineer with Memory controllers
Core
Design and validate DDR memory controller calibration solutions, integrating RTL logic and firmware routines into system-level validation environments for AMD's DDR IPs and custom IPs.
Role type
Senior RTL Design Engineer (Memory Controllers)
Builds
DDR memory controller calibration solutions, firmware routines, and algorithmic flows for AMD's system-level validation and bring-up environments.
Domain
Semiconductor / Memory Subsystems (DDR4, DDR5, LPDDR)
Required skills
RTL design (Verilog/SystemVerilog), memory controller calibration, firmware development (C), system-level architecture (AXI/AHB), circuit timing/STA, validation planning, PVT analysis, version control (Perforce/Git), lab tools (oscilloscopes/logic analyzers)
Preferred skills
Embedded experience, knowledge of JEDEC standards, experience with memory PHYs from different IP vendors, familiarity with high-speed lab tools
Technologies
Verilog, SystemVerilog, C, AXI, AHB, Perforce, Git, DDR4, DDR5, LPDDR
Responsibilities
Design and implement robust firmware solutions for DDR memory controller calibration; Develop and refine calibration algorithms for reliable memory initialization under varying PVT conditions; Create and execute validation plans to verify correctness and performance of calibration firmware and custom IPs; Collaborate with silicon design, verification, and system engineering teams to align firmware with hardware capabilities; Stay updated with emerging DDR technologies and propose innovative solutions to improve calibration robustness and reduce boot time
Seniority
Senior, hands-on IC
