Silicon Design Verification Engineer
Core
Create and enhance verification environments for complex processor IP designs using UVM and System Verilog, ensuring functional correctness and coverage closure.
Role type
IC silicon design verification engineer
Builds
Processor IP blocks and subsystems for AMD SoCs
Domain
Semiconductor / Digital Logic / Processor Architecture
Required skills
System Verilog, UVM, C, Python scripting, formal verification (SVA), constrained-random testing, clock gating verification
Preferred skills
RTL implementation, computer organization/architecture, PCIE protocol, AMBA AXI protocol, performance verification, power-aware verification
Technologies
UVM, System Verilog, SVA, Python, formal tools
Responsibilities
Create test plans for complex IP designs; Design testbenches in System Verilog and UVM; Debug tests with design engineers to close coverage; Coordinate with RTL engineers for clock gating logic; Monitor verification quality metrics (pass rates, code coverage, functional coverage)
Seniority
Mid-level IC engineer
