SerDes RTL Design Engineer
Core
Develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes for AMD processors.
Role type
Senior RTL Design Engineer (SerDes/High-Speed I/O)
Builds
High-speed SerDes PHY designs (PMA/PCS) and digital blocks for wireline transceivers
Domain
Semiconductor / High-Speed Digital Design
Required skills
Verilog/System Verilog, RTL design, micro-architecture, design checker tools (LINT/CDC/RDC), static timing analysis, low power design, PPA analysis, behavioral modeling, multi-clock domain design
Preferred skills
SerDes PHY (PMA/PCS) experience, high-speed I/O protocol knowledge, mixed signal design, Python/Perl/TCL scripting
Technologies
Verilog, System Verilog, LINT, CDC, RDC, Python, Perl, TCL
Responsibilities
Micro-architect high-speed SerDes PHY design, design digital blocks (calibration, DSP, CDR), apply low power techniques, verify functionality with test benches, run design checker tools, support functional verification and debug, collaborate on pre-tape out sign-off and silicon bring-up
Seniority
Mid-to-Senior, hands-on IC
