SDC, Synthesis and STA Engineer
Core
Plan and execute front-end implementation of IPs and SoCs, owning SDC development, generation, verification, and timing closure.
Role type
Senior IC SDC, Synthesis, and STA Engineer
Builds
Front-end implementation of IPs, SS, and SoCs
Domain
Semiconductor / Digital IC Design
Required skills
SDC development, SDC generation, verification, promotion/demotion, equivalence checking, synthesis, LEC, CLP, prelayout STA, postlayout STA, timing closure, Lint, CDC, RTL & Netlist static checks, DFT concepts, low power design, complex clocking, debugging
Preferred skills
Experience with firsthail, excellicon, or TCM, top-level or SoC level experience, scripting and automation, interest in AI
Technologies
firsthail, excellicon, TCM, Lint, CDC
Responsibilities
Own constraints and SDC development for IPs, SS, and SoCs; Collaborate with designer and PNR teams to achieve closure; Plan and execute tasks per schedule; Debug and resolve technical issues
Seniority
Senior, hands-on IC
