Silicon Design Engineer - Technical Lead
Core
Designing next-generation microprocessors and chiplet interconnect technologies (UCIe, UALink) for servers, PCs, graphics cards, and VR sets.
Role type
Senior IC Silicon Design Engineer (Technical Lead)
Builds
High-performance die-to-die interconnect IP and micro-architecture modules
Domain
Semiconductor / VLSI / Chiplet Interconnect
Required skills
RTL design, micro-architecture development, I/O protocols (USB, PCIe, CXL), digital design, static timing analysis (STA), area/power/performance optimization, debugging/post-silicon bring-up
Preferred skills
Python/Perl scripting, hardware-firmware co-design, synthesis, equivalence checking, clock-domain crossing (CDC) analysis, multi-clock domain design
Technologies
UCIe, UALink, USB, PCIe, CXL, RTL, Python, Perl
Responsibilities
Drive design specifications for chiplet interconnect IP, develop micro-architecture for digital blocks, optimize designs for area/power/performance, collaborate with DFT, verification, and firmware teams
Seniority
Senior, hands-on IC with leadership potential
