RTL Design & Validation Lead with DDR protocols exp
Core
Plan, build, and execute design and validation of new and existing features for AMD's DDR IPs and custom IPs, focusing on memory controller calibration solutions.
Role type
Senior RTL Design & Validation Lead (DDR)
Builds
DDR memory controller calibration solutions (RTL logic, firmware routines, algorithmic flows) for AMD's system-level validation and bring-up environments.
Domain
Semiconductor / Memory Subsystem / DDR Technologies
Required skills
RTL design (Verilog/SystemVerilog), DDR standards (DDR4/DDR5/LPDDR/JEDEC), memory controller calibration algorithms, system-level validation, firmware development (C), silicon bring-up and debug, cross-functional collaboration
Preferred skills
Circuit timing/STA, embedded systems experience, memory PHY training software, lab tools (oscilloscopes, logic analyzers), version control (Perforce/Git), geographically dispersed team experience
Technologies
Verilog, SystemVerilog, C, Perforce, ICManage, Git, DDR4, DDR5, LPDDR, JEDEC, AXI, AHB
Responsibilities
Design and implement robust firmware solutions for DDR memory controller calibration; Develop and refine calibration algorithms for reliable memory initialization under PVT conditions; Create and execute validation plans to verify correctness and performance of calibration firmware and custom IPs; Perform system-level bring-up and debug activities to resolve memory training and stability issues; Collaborate with silicon design, verification, and system engineering teams to align firmware with hardware capabilities
Seniority
Senior, hands-on IC
