Sr. RTL Design Engineer
Core
Design and implement RTL for complex digital and mixed-signal blocks, supporting IP development for Silicon implementation and first-time-right SW solutions.
Role type
Senior RTL Design Engineer (ASIC/SoC)
Builds
Next-gen processors, FPGA devices, and adaptive/embedded computing platforms
Domain
Semiconductor / VLSI / Digital Design
Required skills
RTL design (Verilog, SystemVerilog), ASIC/SoC development flow, Physical design (synthesis, place-and-route, STA), DFT implementation, UVM/OVM verification, Scripting (Perl, Tcl, Shell, Python), High-speed interfaces (HBM, SerDes, PCIe)
Preferred skills
FPGA architecture knowledge, Mentorship, Cross-functional collaboration
Technologies
Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, Cadence tool suites
Responsibilities
Design RTL for complex digital and mixed-signal blocks; Support physical design activities including synthesis, DFT, place-and-route, and STA; Collaborate with verification teams for block-level verification; Utilize scripting languages to maintain and develop design automation flows; Partner with cross-functional teams to resolve technical issues and achieve milestones
Seniority
Senior, hands-on IC
