CPU RTL Power, Clocking, Reset Design Engineer
Core
Design, document, implement, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL for AMD's Core Complex Cache Hierarchy to optimize timing, testability, and physical implementation.
Role type
Senior IC RTL Design Engineer (Power, Clocking, Reset)
Builds
Core Complex Cache Hierarchy connecting compute cores and L2 caches with coherency fabric
Domain
Semiconductor / CPU Microarchitecture
Required skills
RTL design, Verilog HDL, scripting, clocking architecture, power management, reset logic, clock-domain crossing, voltage-domain management, SoC development, tapeout closure, cross-functional collaboration, mentorship
Preferred skills
High-performance CPU product architecture, system management, voltage management and distribution, complex architectural interactions
Technologies
Verilog HDL, RTL design tools, SoC development environments
Responsibilities
Collaborate with Architecture, Physical Design, Verification, and Design-for-Test teams; Solve complex architectural interactions across global IP and SoC teams; Improve CPU design quality, performance, power, and area; Solve complex design and tool challenges; Guide, mentor, and develop engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
