Lead Design Verification
Core
Lead end-to-end verification for complex digital IPs, subsystems, and SoC designs, ensuring first-pass silicon success.
Role type
Senior IC design verification engineer (DisplayPort/SoC)
Builds
High-quality, reliable semiconductor products (digital IPs, SoCs)
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random verification, assertion-based verification, functional coverage, simulation debugging, root cause analysis, protocol compliance analysis, team mentoring, automation scripting
Preferred skills
PCIe, USB, HDMI, MIPI, Ethernet, DDR protocol verification, Formal Verification, emulation/FPGA prototyping, low-power verification (UPF/CPF), CI/CD workflows, SoC integration (AMBA protocols)
Technologies
SystemVerilog, UVM, Python, Perl, Shell, TCL, EDA simulation tools
Responsibilities
Lead end-to-end verification activities for complex digital IPs, subsystems, and SoC designs; Develop comprehensive verification plans based on design specifications; Build scalable, reusable, and modular verification environments; Create constrained-random testbenches, assertions, scoreboards, and functional coverage models; Verify DisplayPort IPs and interfaces across multiple protocol versions; Collaborate with design, architecture, firmware, validation, and physical design teams; Perform simulation, debugging, root cause analysis, and issue resolution; Drive coverage closure by monitoring functional, code, and assertion coverage metrics; Mentor junior verification engineers; Support post-silicon validation teams in debugging silicon issues
Seniority
Senior, hands-on IC with leadership responsibilities
