RTL Design Manager
Core
Manage a team designing and implementing high-performance, low-power System-on-Chips (SOCs) and SOC Chiplets for next-generation compute acceleration platforms.
Role type
Senior IC SOC Design Manager
Builds
High-performance, low-power SOCs and SOC Chiplets for a wide range of applications and customer-specific products
Domain
Semiconductor / Digital IC Design
Required skills
RTL design (Verilog/System Verilog), SOC/ASIC design, DFT, timing closure, microarchitecture development, team management, project planning, cross-functional stakeholder management
Preferred skills
AI adoption for process improvement, scripting (TCL/Python/Perl), Linux/Windows fluency
Technologies
Verilog, System Verilog, Spyglass, Questa CDC, Cadence Conformal, VCS, Synopsys Design Compiler, Synopsys Primetime, UPF, Perforce, IC Manage, Git
Responsibilities
Team management (hiring, coaching, reviewing), project planning and execution tracking, design reviews, tapeout checklists, process improvement
Seniority
Senior, hands-on IC
