Silicon Design Engineer
Core
Design host controller IP for next-generation high-speed I/O technologies (up to 40 Gb/s) to maintain AMD's leadership in I/O architecture.
Role type
Senior Silicon Design Engineer (IP)
Builds
Host controller IP blocks for high-speed I/O interfaces
Domain
Semiconductor / High-speed I/O / Digital Logic
Required skills
Verilog HDL, RTL design, I/O architecture, USB 3/4/Thunderbolt, PCIe, AMBA, digital IP design, functional verification, mentoring
Preferred skills
AI-assisted design, complex problem solving, independent work, project planning
Technologies
Verilog, USB 3, USB4, Thunderbolt, PCIe, AMBA
Responsibilities
Develop RTL code for IP blocks, ensure design reusability across product lines, solve complex technical problems, make technical decisions, coach junior engineers
Seniority
Senior, hands-on IC
