Design Verification Engineer
Core
Drive verification efforts for DDR interfaces (DFI, DDR5, LPDDR5/LPDDR6) in server memory products, ensuring alignment between hardware, firmware, BIOS, and software.
Role type
Senior IC design verification engineer (memory protocols)
Builds
Server memory products (DIMMs) with advanced DDR interfaces
Domain
Semiconductor / High-performance computing / Memory systems
Required skills
SystemVerilog, UVM, C/C++, Python, Perl, RTL understanding, micro-architecture knowledge, formal verification methods, VIP/BFM development, simulation environments, functional coverage modeling
Preferred skills
GLS, NLP, XPROP simulation experience, system Verilog assertions/constraints/coverage expertise, mentorship capabilities
Technologies
SystemVerilog, UVM, Python, Perl, GLS, NLP, XPROP
Responsibilities
Develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems; Comprehend PHY interactions across HW, FW, BIOS, and SW; Engage in cross-functional discussions with architects and design engineers for planning and debug; Contribute to verification methodology and knowledge sharing; Support Post-Si teams for performance, power, and functional issue resolution
Seniority
Senior, hands-on IC with mentorship responsibilities
