Senior High Speed IO Validation Engineer
Core
Own characterization and qualification of high-speed I/Os (PCIe, NVLink, UCIe, USB, UFS, Ethernet) on new silicon for datacenter, AI, and client markets.
Role type
Senior IC high-speed I/O validation engineer
Builds
High-volume production GPUs, SoCs, and CPUs
Domain
Semiconductor hardware validation (high-speed serial links)
Required skills
High-speed serial link protocols (PCIe, NVLink, UCIe, CXL), SERDES architecture, Signal Integrity (SI) and Power Integrity (PI) fundamentals, Lab instrumentation (DSOs, BERTs, VNAs, protocol analyzers), Python-based test automation, Root-cause analysis, Manufacturing yield assessment
Preferred skills
PCIe Gen5/Gen6 or NVLink validation experience, SERDES or mixed-signal/analog circuit design experience, Translating rack-environment conditions to silicon/board characterization, AI productivity tools usage
Technologies
PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet, CoWoS, interposer, substrate, Python, DSOs, BERTs, VNAs, TDR
Responsibilities
Develop and execute validation test plans for silicon and SoC-level HSIO features; Drive power characterization and optimization across IO interconnects; Drive systematic root-cause analysis for complex HSIO bugs; Assess manufacturing and yield implications of HSIO margin distributions; Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure
Seniority
Senior, hands-on IC
