SRAM Circuit Design Engineer - New College Grad 2026
Core
Designing embedded SRAM macros and developing compilers to automate their assembly and validation for NVIDIA's SOC design partners.
Role type
Senior IC SRAM circuit design engineer
Builds
SRAM macros and compilers for System-on-Chip (SOC) designs
Domain
Semiconductor / Digital Integrated Circuits
Required skills
Transistor-level circuit design, SRAM macro design (single/dual-port, register files), layout implementation, physical and logical verification, debug, FinFET and nanosheet process knowledge, self-timed logic, sense-amplifiers, Cadence Virtuoso
Preferred skills
AI coding and analysis tools (Codex, Claude Code), silicon testing/debug experience
Technologies
Cadence Virtuoso, FinFET, nanosheet
Responsibilities
Design transistor-level SRAM circuits, supervise layout implementation, perform physical and logical verification, debug SRAM macros, develop SRAM compilers for automated assembly and validation, collaborate with SOC design partners to achieve performance and cost goals, guide silicon test and characterization efforts
Seniority
Entry-level (New College Grad 2026)
