Senior DFT Engineer
Core
Design and prototype breakthrough Test Architectures for reticle-sized, multi-chiplet products, spanning RTL to verification to post-silicon ATE bring-up.
Role type
Senior IC Design-For-Test (DFT) Engineer
Builds
Next-generation silicon platforms (2.5D/3D AI data center, Gaming, Enterprise GPUs, complex SOCs)
Domain
Semiconductor / VLSI / Hardware Testing
Required skills
ATPG (Automatic Test Pattern Generation), DFT methodologies, ATE bring-up, RTL design, VLSI architecture, EDA tool collaboration, coverage analysis, pattern generation, mentoring
Preferred skills
2.5D/3D ICs, multi-chiplet architectures, reticle-sized designs, EDA tool flow development, Silicon testing, AI/automation programming
Technologies
ATPG tools, ATE, EDA tools, RTL, VLSI
Responsibilities
Develop and deploy industry-leading test methodologies; Co-architect novel DFT strategies; Own the full ATPG lifecycle; Collaborate with EDA vendors and internal CAD teams; Guide and mentor junior engineers
Seniority
Senior, hands-on IC
