Design Verification Engineer (RDSS Intern)
Core
Design Verification Engineer for multimedia IP in GPU and SoC chips, developing verification environments, test cases, and coverage.
Role type
Design Verification Engineer (Intern)
Builds
Multimedia IP for GPU and SoC chips
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, C++, Python, TCL, Make, shell scripting, OOP, digital build principles, functional coverage, assertions
Preferred skills
AI Agent development, AI-enabled automation workflows, C++/SystemC modeling, complex verification strategy implementation
Technologies
SystemVerilog, UVM, Python, C++, SystemC, TCL, Make, shell
Responsibilities
Collaborate with Architect, SOC, and IP teams to define verification scope; Engage in test planning; Apply C/SV/UVM methodologies for block and full chip verification; Contribute to verification strategies; Solve complex verification challenges.
Seniority
Intern
