Formal Verification Engineer
Core
Senior Formal Verification Engineer crafting all aspects of GPU clocking, collaborating with frontend and backend teams to architect, design, and validate clocking RTL for consumer graphics, self-driving cars, and AI.
Role type
Senior IC formal verification engineer (hardware/ASIC)
Builds
GPU clocking RTL and verification environments
Domain
Semiconductor hardware design (ASIC/GPU)
Required skills
formal verification methodologies, assertion development, abstraction modeling, RTL debugging, scripting (TCL, Perl, Python), verification flow management
Preferred skills
experience with Jasper Gold or VC Formal, protocol/data transmission verification, complex design analysis
Technologies
Jasper Gold, VC Formal, TCL, Perl, Python
Responsibilities
Write test plans and implement formal techniques (assumptions, assertions, cover properties); Develop abstraction models to obtain full or bounded proofs; Debug RTL to identify failure scenarios and achieve coverage sign-off; Drive tools for optimal performance; Contribute to flow and script development; Collaborate with architects and designers to ensure deliverable quality
Seniority
Senior, hands-on IC
