Physical Design Power Optimization and Modeling Engineer
Core
Power optimization and modeling for high-speed communication chips during RTL-to-GDS physical design development.
Role type
Physical Design Power Optimization Engineer
Builds
High-speed networking silicon chips
Domain
Semiconductor / Networking / Physical Design
Deliverable
production ML models
Required skills
Physical design flow (RTL2GDS), Power optimization, Power estimation, Power modeling, EDA tools (Synopsys, Cadence), Timing closure, Place and route, Noise fixes
Preferred skills
FE design experience, Physical verification, Synthesis, Power and clock distribution
Technologies
Synopsys, Cadence
Responsibilities
Optimize power for blocks/top-level/fc under challenging constraints; Perform synthesis, power/clock distribution, place and route, timing closure, and power/noise fixes; Conduct power estimation and modeling.
Seniority
Mid-level, hands-on IC
