Senior SOC Clocks RTL Design Engineer
Core
Technical lead for clocking logic development on next-generation networking System-On-Chip (SOC), responsible for PLL integration, clock generation, distribution, and domain crossing.
Role type
Senior IC RTL Design Engineer (Clocking)
Builds
Networking System-On-Chips (SOC)
Domain
Semiconductor / Hardware Design
Required skills
Verilog/SystemVerilog RTL design, Clock gating, Clock muxing and dividers, Glitchless clock switching, Reset synchronization, Clock domain crossing (CDC), Static timing analysis (STA), Synthesis optimization, Physical Design (PD) collaboration, Design Verification (DV) coordination
Preferred skills
SOC-level clocking experience, PLL/clock generator integration, High-speed networking design, Low-power design techniques (DVFS, UPF), RTL automation flows
Technologies
Verilog, SystemVerilog, SDC, UPF
Responsibilities
Lead implementation of clocking logic from specification through tape-out and bring-up, Translate clock architecture schemes into verifiable RTL designs, Mentor engineers and set coding standards, Collaborate with Physical Design on clock tree implementation and timing convergence, Partner with Verification on testplans and debug, Support Software teams on clock programming and power flows
Seniority
Senior, hands-on IC
