ASIC Design Engineer, Clocks
Core
Design, architect, and validate high-frequency, low-power clocking RTL for NVIDIA GPUs supporting consumer graphics, self-driving cars, and AI.
Role type
Senior IC ASIC Design Engineer (Clocks)
Builds
GPU clocking RTL and netlists for high-performance silicon
Domain
Semiconductor / ASIC Design / GPU
Required skills
RTL design (Verilog), logic synthesis, Perl/Python scripting, cross-talk/noise analysis, OCV effects understanding, DFT knowledge, on-chip clocking network implementation
Preferred skills
Sub-micron silicon issue expertise, backend flow knowledge, software/silicon debugging
Technologies
Verilog, Perl, Python
Responsibilities
Collaborate with frontend and backend teams to define clocking requirements; design and validate clocking RTL; run and enhance in-house flows for RTL and netlist quality; drive issue resolution; deliver clock information to SOC verification, timing, and DFT teams; debug GPU clock silicon bugs with software and silicon solution teams.
Seniority
Senior, hands-on IC
