CareerPlan

System Verification Co-Design Engineer - Speed and Rel

US, CA, Santa ClaraFull-time$136k2026-07-28 → 2026-11-10
Hybrid

Core

Develop verification infrastructure and automation to characterize and validate system-level speed features for silicon products, leading debug of complex issues to ensure on-time shipment.

Role type

Senior IC system verification engineer (silicon speed & reliability)

Builds

Verification collaterals, automation infrastructure, and debug workflows for silicon speed features

Domain

Semiconductor hardware engineering (silicon verification, speed, power, reliability)

Deliverable

production ML models

Required skills

Silicon bring-up, frequency and power characterization, PPA analysis, tester-to-system correlation, lab instrumentation, Python/Perl scripting, statistical data analysis, AI/LLM workflow integration

Preferred skills

Gaming/automotive/datacenter domain experience, AI-assisted characterization/debug automation, LLM evaluation and prompt engineering

Technologies

Python, Perl, JMP, AI/LLM tools (Claude, Copilot, ChatGPT), Oscilloscopes, Multimeters, DAQs

Responsibilities

Collaborate cross-functionally to co-design system-level speed features; Translate hardware requirements into verification techniques; Perform closed-loop validation correlating silicon behavior against timing simulation; Define and refine pre- and post-silicon bring-up flows; Design automation tools for system speed modeling using AI; Lead debug of complex silicon and system-level defects

Seniority

Senior, hands-on IC