Senior SOC Design Engineer - Networking Group
Core
Design and integrate high-speed communication devices (DPUs and Switch Silicon chips) and complex SoCs for enterprise and HPC applications.
Role type
Senior SOC Design Engineer (Networking)
Builds
Next-generation DPUs and Switch Silicon chips
Domain
Semiconductor / Networking / High-speed interconnects
Required skills
ASIC architecture, Micro-Architecture, RTL design, verification, timing closure, Physical design, C/C++ programming, Python scripting, HW/SW interface definition, synthesis, DFT, RTL Build, Design Automation
Preferred skills
Chip lead technical leadership, RTL coding and debug, performance/power/area analysis, smartNIC experience, high-speed interconnects experience, Perl scripting
Technologies
Verilog/SV, Cadence, Indago, GDB, Perl, Python
Responsibilities
Define project milestones and track them through agile framework; Develop system-level methodologies, tools, and IPs to build subsytems; Integrate project pieces and deliver models for verification at cluster/sub-system/SOC/emulation levels; Collaborate with cross-functional teams on complex cross-functional problems.
Seniority
Senior, hands-on IC
