ASIC Physical Design Engineer, Netlisting - New College Grad 2026
Core
Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block, cluster, and full chip levels, focusing on netlist-related aspects like equivalence checking, asynchronous checking, and logic synthesis.
Role type
ASIC Physical Design Engineer (Netlisting)
Builds
High-performance CPUs, GPUs, and SoCs for AI computing, gaming, and accelerated computing
Domain
Semiconductor / ASIC Design / AI Hardware
Deliverable
production ML models
Required skills
Logic equivalence checking, Formal Verification, RTL/logic design, Clock-domain-crossing checking, MTBF analysis, Logic synthesis, EDA tools (Synopsys/Cadence), Scripting (Perl/TCL/Python)
Preferred skills
AI utilization for workflow improvement, Strong debugging capability
Technologies
Synopsys, Cadence, Perl, TCL, Python, Make
Responsibilities
Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.; Help in ECO generation and implementation.
Seniority
Junior, New College Grad 2026
