Senior Package Modeling Engineer
Core
Conduct Finite Element Analysis (FEA) to assess stress, warpage, and thermo-mechanical behavior in advanced semiconductor packaging platforms.
Role type
Senior IC mechanical simulation engineer (semiconductor packaging)
Builds
Advanced semiconductor packaging platforms (flip-chip, 2.5D/3D IC, CoWoS-R, CoWoS-L)
Domain
Semiconductor manufacturing / Thermal-mechanical engineering
Required skills
Finite Element Analysis (FEA), ANSYS, Abaqus, COMSOL, thermal-mechanical interactions, reliability failure modes, JEDEC standards, accelerated life testing, semiconductor packaging architecture
Preferred skills
MS or PhD in Mechanical Engineering or Materials Science, 5+ years FEA experience, cross-functional collaboration
Technologies
ANSYS, Abaqus, COMSOL
Responsibilities
Conduct FEA to assess stress, warpage, and thermo-mechanical behavior; Evaluate new materials and interconnect concepts for packaging roadmaps; Analyze material properties and their impact on package reliability; Establish modeling approaches and interpret simulation results; Collaborate with cross-functional teams to ensure robust package builds; Document modeling methodologies and present findings.
Seniority
Senior, hands-on IC
