Senior Mixed Signal Design Engineer
Core
Designing mixed-signal/analog circuits for high-speed memory I/O interfaces in advanced CMOS FinFET processes.
Role type
Senior IC mixed-signal design engineer (high-speed memory)
Builds
High-speed DRAM SerDes solutions (LPDDR5/6, DDR4/5, GDDR5/6/7, HBM3/4)
Domain
Semiconductor / High-speed memory interfaces
Required skills
Mixed-signal/analog circuit design, High-speed DRAM SerDes design, Deep submicron CMOS FinFET process knowledge, Device reliability (ESD, Latch-Up), System-level timing budget analysis, Cadence custom design tools, Circuit simulators (Hspice, XA, FineSim, Spectre)
Preferred skills
Package substrate and board development, Power delivery design, Verilog, Nanotime, Matlab, Silicon debug with lab equipment
Technologies
Cadence, Hspice, XA, FineSim, Spectre, Verilog, Nanotime, Matlab
Responsibilities
Design mixed-signal/analog circuits for high-speed memory I/O interfaces, Solve circuit design challenges in latest CMOS FinFET processes, Take designs through productization, Work with multi-functional teams to optimize design, Contribute to architecture definition of next-generation memory systems
Seniority
Senior, hands-on IC
