Senior ASIC Engineer, Power Integrity
Core
Design innovative power delivery and power management solutions for deep submicron processor designs, ensuring reliability, performance, and stability through modeling and simulation.
Role type
Senior IC ASIC engineer (power integrity)
Builds
Processor designs in deep submicron technologies
Domain
Semiconductor / Analog and Mixed Signal (AMS) / Power Integrity
Deliverable
production ML models
Required skills
Power delivery network (PDN) modeling, Analog and digital circuit simulation, EDA tools (Cadence Virtuoso, Allegro, VCS, HSpice, Spectre), Verilog/VerilogA, Mentor/technical leadership
Preferred skills
Ansys Siwave/HFSS/Sigrity, Control loops and feedback systems, Scripting (Perl, Tcl, Python, Skill)
Responsibilities
Participate in innovative Processor design in deep submicron technologies, Work as part of a global circuits team to design innovative power delivery and power management solutions, Build models of analog and digital circuits and systems in a variety of environments, Perform detailed block-level and system-level simulations to ensure good reliability, performance, and stability of the designs, Be a mentor/technical lead for junior team members
