Senior Digital Design Verification Engineer - Hardware
Core
Verify digital design, golden models, and micro-architecture of cutting-edge SerDes IPs to enable gaming, AI, deep learning, and autonomous driving.
Role type
Senior IC digital design verification engineer (SerDes)
Builds
High-speed SerDes IPs consumed by standard and proprietary protocols
Domain
Hardware verification / High-speed serial interfaces
Deliverable
production ML models
Required skills
SystemVerilog, UVM, coverage-driven verification, random stimulus, assertion-based verification, bus functional modeling, micro-architecture understanding
Preferred skills
PCI Express, USB, SATA protocols, mixed-signal design verification, analog circuit modeling, Perl, Python, C/C++
Technologies
UVM, SystemVerilog, simulation and debug tools
Responsibilities
Verify digital design and implementation of SerDes IPs; Build reusable bus functional models, monitors, checkers, and scoreboards; Define verification scope and develop verification infrastructure; Write and implement test plans for product shipment schedules; Collaborate with architects, designers, and pre/post silicon teams
Seniority
Senior, hands-on IC
