Senior Chip Design Verification Engineer
Core
End-to-end Unit-Level verification of complex chip blocks for high-speed communication devices, ensuring functional and micro-architectural requirements are met.
Role type
Senior IC chip design verification engineer
Builds
High-speed networking silicon chips
Domain
Semiconductor / Networking
Required skills
UVM, SystemVerilog, Specman, HDL (Verilog/VHDL), verification planning, coverage closure, assertion development, corner case analysis
Preferred skills
Experience in verification of complex scenarios, feature interactions, error flows, performance-related behavior
Technologies
Specman, UVM, SystemVerilog, Verilog, VHDL
Responsibilities
Own end-to-end Unit-Level verification from planning to coverage closure; Develop verification strategies, environments, checkers, and assertions; Drive verification of complex scenarios including feature interactions and corner cases; Collaborate with architecture teams to identify design gaps and ensure verifiability
Seniority
Senior, hands-on IC
