Senior System Architect, High-Speed Interconnects
Core
Lead the end-to-end definition of high-speed interconnect systems for next-gen AI platforms, focusing on 224G/448G PAM4 lanes and beyond.
Role type
Senior System Architect (High-Speed Interconnects)
Builds
NVLink and InfiniBand/Ethernet fabrics for AI data centers
Domain
Semiconductor hardware, high-speed interconnects, data center infrastructure
Deliverable
production ML models
Required skills
Signal Integrity (SI), Channel Operating Margin (COM), BER, FEC, crosstalk analysis, PCIe Gen 6/7, Ethernet 800G/1.6T, OSFP/QSFP-DD/SFP-DD form factors, DAC/ACC/AOC architectures, Silicon Photonics, CPO, MPO/APC fiber architectures
Preferred skills
Experience with 112G and 224G PAM4 environments, ability to predict technology bottlenecks 3–5 years in advance, multi-functional influence across Software/Hardware/Thermal teams
Technologies
NVLink, InfiniBand, Ethernet, PCIe, Co-Packaged Optics (CPO), Silicon Photonics, OSFP, QSFP-DD, SFP-DD, MPO, APC
Responsibilities
Architectural definition of high-speed interconnect systems, technology roadmap evaluation and selection, system co-design with ASIC/Thermal/PCB teams, standardization leadership in industry bodies, vendor ecosystem management, performance modeling and trade-off analysis
Seniority
Senior, hands-on IC
