Senior Physical Design Methodology Engineer, Innovus Flows
Core
Developing innovative physical design methodologies for GPU, CPU, Network processors, and SOC implementation to improve PPA (Power, Performance, Area) and runtime on advanced technology nodes.
Role type
Senior IC physical design methodology engineer
Builds
GPU, CPU, Network processors, and SOC chips for Datacenter AI, HPC, Networking, Robotics, and Autonomous driving
Domain
Semiconductor physical design and EDA
Deliverable
production ML models
Required skills
Physical design flow development, PPA optimization, STA, extraction, timing and RC correlation, low power design (UPF), EM and IR analysis, synthesis flows, power distribution networks, EDA tool scripting (TCL, Perl, Python, C++)
Preferred skills
AI/ML approaches to CAD, data analysis/ML libraries (NumPy, SciPy, scikit-learn, PyTorch), Cadence EDA tool suite (Innovus, Genus, Tempus, Quantus, Joules)
Technologies
Innovus, Genus, Tempus, Quantus, Joules, NumPy, SciPy, scikit-learn, PyTorch, TCL, Perl, Python, C++, UPF, FSDB, SAIF
Responsibilities
Develop innovative physical design methodologies for implementation of processors and SOC with emphasis on PPA and runtime improvement; Work with internal and external partners to drive tool and methodology improvements; Use AI/ML approaches to CAD to improve design performance and turnaround time
Seniority
Senior, hands-on IC
