Senior Validation Architect, NVLink
Core
Define next-generation chip interconnects and protocols (NVLink) by developing architectural modeling and testing requirements, integrating functional models into fullchip/multichip environments, and shepherding designs through the product lifecycle.
Role type
Senior IC Validation Architect (chip interconnects)
Builds
Next-generation NVLink communications standards and products
Domain
Semiconductor / Chip Interconnects / Hardware Architecture
Required skills
ASIC design processes, C++, Python, SystemC modeling, functional modeling, testplan development, debugging in FW/SW environments, IP model integration, processor/I/O architecture
Preferred skills
SystemC modeling
Technologies
C++, Python, SystemC, Makefile
Responsibilities
Define architectural modeling and testing requirements for new NVLink features; Drive architectural testing requirements into lower level testbenches; Implement functional models and integrate them into fullchip and multichip environments; Support and debug tests in model, emulation, and post-silicon environments
Seniority
Senior, hands-on IC
