Senior SRAM Circuit Design Engineer
Core
Designing embedded SRAM macros and developing automated compilers for SRAM assembly and validation for NVIDIA GPUs.
Role type
Senior IC SRAM circuit design engineer (compiler development)
Builds
SRAM macros and automated compilers for NVIDIA SOC design partners
Domain
Semiconductor / Digital Integrated Circuits
Required skills
Transistor-level circuit design, SRAM macro design (single/dual-port/register file), layout implementation, physical and logical verification, debug, Python scripting, advanced FinFET process knowledge
Preferred skills
MSEE or PhD, Cadence schematic and layout capture tools, silicon testing/debug experience
Technologies
Python, Cadence
Responsibilities
Transistor-level circuit design and supervising layout implementation of embedded SRAM macros, Envisioning and coding efficient ways to automate simultaneous assembly and validation of multiple unique SRAM macros, Exploring potential of future process nodes to achieve optimal power, performance, and area characteristics, Collaborating with SOC design partners to achieve performance and cost goals and guiding silicon test and characterization efforts
Seniority
Senior, hands-on IC
