CPU Architecture and RTL Design Engineer
Core
Define, implement, and integrate Clocking, Reset, and Power for AMD's next-generation CPU caches and cores.
Role type
Senior IC CPU Architect/RTL Design Engineer
Builds
High-performance, high-frequency, power-efficient server, desktop, and laptop CPUs
Domain
Semiconductor / CPU Design
Required skills
CPU architecture, RTL design, Verilog HDL, Static Timing Analysis, CDC/Gate CDC, Static Power analysis, Clock/Power Domain Crossing, Power Management
Preferred skills
Shared cache design, Last Level Cache (LLC) design, Physical design collaboration, Verification team collaboration
Technologies
Verilog HDL
Responsibilities
Define and implement CPL microarchitecture for AMD CPUs; Deliver designs from concept through tapeout; Drive design closure with timing and power analysis; Innovate for high performance and efficiency on caches, fabrics, and interfaces.
Seniority
Senior, hands-on IC
