Leadership Role - DFT
Core
Lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs from architecture definition through manufacturing ramp.
Role type
Principal Member of Technical Staff (PMTS), hands-on IC technical leader
Builds
Production-quality test solutions and robust DFT methodologies for next-generation SoCs
Domain
Semiconductor / SoC Design / Manufacturing Test
Required skills
ATPG strategy and execution, scan methodologies, pattern validation, DFT architecture, tester correlation, root-cause analysis, cross-functional leadership, automation scripting
Preferred skills
Multi-million gate SoC experience, hierarchical ATPG, compression techniques, silicon diagnosis, yield improvement, geographically distributed team leadership
Technologies
Tessent, Modus, TestMAX, TetraMAX, Python, Perl, Tcl, Shell, STIL, WGL
Responsibilities
Define ATPG methodologies and coverage closure plans, generate and validate ATPG patterns, drive tester efficiency and cost reduction, partner with RTL/Physical Design/ATE teams, lead pattern validation across environments, support silicon bring-up and yield learning, mentor junior engineers
Seniority
Principal, hands-on IC with mentorship responsibilities
