RTL Digital Design Engineer
Core
Design and develop RTL for AMD's PCI Express (PCIe) IP used across next-generation server, client, GPU, and semi-custom products.
Role type
Senior IC RTL Digital Design Engineer
Builds
Next-generation PCI Express (PCIe) IP for AMD's server, client, GPU, and semi-custom products
Domain
Semiconductor / High-speed interface protocols
Required skills
ASIC/SoC digital design, RTL development (Verilog/SystemVerilog), synchronous digital design principles, multi-clock domain implementations, lint/CDC/timing analysis, low-power design techniques, silicon validation and hardware debug, high-speed interface protocols (PCIe, USB, SATA, Ethernet)
Preferred skills
Master's degree in EE/CS/Engineering Science, experience with technical specifications and microarchitecture documentation, familiarity with ASIC design flows, experience collaborating across architecture, verification, physical design, and silicon validation teams
Technologies
Verilog, SystemVerilog, PCIe, USB, SATA, Ethernet, logic analyzers, oscilloscopes
Responsibilities
Design and develop RTL for PCIe IP, define and implement microarchitectural features, drive high-quality RTL development with focus on timing closure and CDC analysis, implement and optimize low-power design techniques, collaborate with verification engineers for simulation and debug, participate in silicon bring-up and post-silicon debugging, support design reviews and improve design methodologies
Seniority
Senior, hands-on IC
