FPGA/ASIC Design Engineer (Silicon Engineering)
Core
Designing and optimizing next-generation FPGAs and ASICs for Starlink satellite and ground infrastructure to enable global broadband connectivity.
Role type
Senior IC FPGA/ASIC Design Engineer
Builds
Production FPGAs and ASICs for Starlink satellites and ground systems
Domain
Aerospace / Satellite Communications / Silicon Design
Required skills
RTL Design (SystemVerilog, Verilog, VHDL), SoC integration, Power/Performance/Area optimization, EDA tools (VCS, Questa, Vivado, Quartus), AXI/AHB/APB protocols, PCB debugging
Preferred skills
Python, C/C++, Bash, DSP/modem design, Master's degree in EE/CS
Technologies
Verilog, SystemVerilog, VHDL, VCS, Questa, Xilinx Vivado, Altera Quartus II, AXI, AHB, APB
Responsibilities
Design ASICs and/or FPGAs implementing complex SoC blocks, Optimize designs for power/performance/area, Participate in full design lifecycle from architecture to validation, Build tools to analyze on-orbit data, Engage in high-level architectural design for test systems, Collaborate with software engineers on production software
Seniority
Mid-Senior, hands-on IC
