Logic Design Engineer
Core
Design and develop high-speed mixed-signal IO architectures and RTL for AMD's next-generation computing products.
Role type
Senior IC logic design engineer (mixed-signal/high-speed IO)
Builds
High-speed IO interfaces (DDR, GDDR, HBM, SERDES) for AI, data centers, PCs, and gaming
Domain
Semiconductor / Mixed-signal digital design
Required skills
Verilog RTL, ASIC design flows, microarchitecture specification, timing closure, power optimization, silicon bring-up, analog mixed-signal design, high-speed interface protocols, multi-clock/power domain design, ASIC CAD tools
Preferred skills
Analog mixed-signal design experience, high-speed SERDES, multi-domain clock/power design, behavior modeling for analog circuits
Technologies
Verilog, ASIC CAD tools, DDR, GDDR, HBM, SERDES, UPF
Responsibilities
Analyze complex digital design problems and propose architecture solutions, Develop Verilog RTL and Functional Behavioral Models, Drive/develop ASIC design flows and scripts, Create microarchitecture specifications, Work with Design Verification and Physical Design teams, Deliver improvements, optimization, and power-saving enhancements, Support silicon bring-up and diagnostics
Seniority
Mid-to-Senior, hands-on IC
