AMS Verification Engineer (RFIC Engineering)
Core
Developing verification flows, testbenches, and behavioral models for next-generation RFICs and RF-SoCs used in Starlink satellites and ground infrastructure.
Role type
AMS Verification Engineer (Silicon Engineering)
Builds
RFICs and RF-SoCs for Starlink satellite and ground systems
Domain
Aerospace / Satellite Communications / Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
AMS simulation tools, annotated gate-level simulation, System-Verilog, UVM, Python, Verilog-A/AMS behavioral modeling, analog circuit fundamentals, digital circuit blocks understanding
Preferred skills
Master's or PhD in engineering, experience with LDOs, bandgaps, DACs, ADCs, mixers, RF amplifiers, oscillators, PLLs, RTL and gate-level netlists
Technologies
System-Verilog, UVM, Python, Verilog-A, AMS simulators
Responsibilities
Develop and own analog-on-top and digital-on-top design verification flows for full-chip simulations, create testbenches for critical RFIC/SoC interfaces, collaborate with designers to improve simulation speed/accuracy for mixed-signal IPs, create behavioral models for analog/mixed-mode circuit blocks, work with ATE test engineering to develop testplans, run EM/IR simulations
Seniority
Entry to Mid-level, hands-on IC