Hardware Validation and Debug Engineer - DDR
Core
Hardware Validation and Debug Engineer for LPDDR5 memory interfaces and system platforms, ensuring correct operation under all conditions through manual testing and debugging.
Role type
Hardware Validation and Debug Engineer
Builds
AI computing system platforms and silicon devices
Domain
Semiconductor hardware, AI data centre infrastructure, high-speed memory interfaces
Deliverable
production ML models | product features | infrastructure
Required skills
LPDDR5 validation and tuning, signal integrity analysis, DDR training and margin analysis, protocol-level debugging, root-cause analysis, low-level system integration, board bring-up, subsystem debug, issue resolution across hardware/firmware domains, lab instrumentation (oscilloscopes, BERT, VNA/TDR), LPDDR5 compliance testing
Preferred skills
PCBA and system level technologies, Ethernet validation, PCIe, ATE systems knowledge, scripting automation (Python, LabView, BASH)
Technologies
LPDDR5, SPI, I2C, I3C, UART, Python, LabView, BASH, High-bandwidth oscilloscopes, BERT systems, VNA/TDR
Responsibilities
Perform validation and debug for new hardware platforms, debug PCB/power/signal integrity/interface issues, validate high-speed and slow-speed memory interfaces, support LPDDR5 initialization and timing optimization, analyse timing margins and eye diagrams, identify root causes and drive corrective actions, create bring-up documentation and test procedures
Seniority
Mid-level, hands-on IC
