RTL Design Engineer
Core
Lead technical development of complex Silicon IP solutions (PCIe, NVMe, Networking) from architecture definition through ASICization for AI, data centers, and embedded systems.
Role type
Senior IC ASIC RTL Design Engineer (Member Technical Staff)
Builds
Complex programmable logic based silicon designs and IP subsystems
Domain
Semiconductor / Hardware Design
Required skills
Verilog RTL design, IP Architectural definition, u-Architecture development, VCS simulation, Perl/Shell scripting, Design for Test methodologies, PCIe/NVMe/Ethernet/TCP/IP/RDMA IP development, Cross-functional team leadership
Preferred skills
Complex silicon tapeout experience, Senior technical review capabilities, Technical mentorship
Technologies
Verilog, VCS, Perl, Shell
Responsibilities
Define u-architecture from architecture definition, Evaluate and execute design and development plans for IPs, Perform RTL design and IP Integration, Act as senior technical reviewer for u-architecture and implementation reviews, Develop comprehensive testing plans including Compliance and Interop testing, Critically review Design Implementations and Verification plans, Mentor junior engineers
