SoC Physical Design Implementation Lead
Core
Lead full-chip physical design strategy and execution for AMD's next-generation Instinct AI and data center processors, focusing on complex SoC architectures with chiplets and 3D stacking.
Role type
Senior IC SoC Physical Design Implementation Lead
Builds
Next-generation Instinct AI and data center processors
Domain
Semiconductor / SoC Physical Design
Deliverable
production ML models
Required skills
SoC physical design strategy, floorplanning, placement, CTS, routing, timing sign-off, PPA optimization, 3D stacking integration, AI-driven automation, Tcl/Perl/Shell scripting, CAD tools (Synopsys, Cadence, Siemens)
Preferred skills
Advanced process nodes (3nm/2nm), static timing analysis (STA), clock distribution, physical verification, power optimization, AI/ML techniques for design efficiency
Technologies
Synopsys, Cadence, Siemens (Mentor Graphics), Tcl, Perl, Shell, 3nm, 2nm
Responsibilities
Lead SoC-level Physical Design strategy and execution including floorplanning, placement, CTS, routing, and tapeout; Drive power optimization and PPA closure for advanced nodes; Develop and implement advanced physical design methodologies including AI-driven automation; Collaborate with cross-functional teams to meet performance and schedule goals; Provide technical leadership and mentorship to physical design teams
Seniority
Senior, hands-on IC with leadership responsibilities
