STA / Synthesis Engineer (Staff / Sr. Staff / Principal)
Core
Own RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon.
Role type
Staff/Sr. Staff/Principal STA/Synthesis Engineer
Builds
Complex compute, CPU, VPU, and low-power cores targeting advanced process technologies
Domain
Semiconductor / High-Performance Computing / AI
Deliverable
production ML models
Required skills
RTL-to-gate synthesis, static timing analysis, timing closure, power optimization, constraint management, ECO flows
Preferred skills
ASIC/SoC design expertise, advanced process technology knowledge, cross-functional collaboration
Technologies
RTL, DFT, physical design, CAD, verification tools
Responsibilities
Drive implementation quality, timing convergence, and sign-off readiness; influence synthesis strategy and implementation best practices; collaborate with RTL, architecture, and product engineering teams to meet PPA and Cost targets.
