ASIC Design Engineer - Networking/ DPU/ AI Systems
Core
Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads, covering the full lifecycle from RTL architecture to tapeout and mass production.
Role type
Senior IC ASIC Design Engineer (Networking/DPU)
Builds
High-performance networking systems and DPU ASICs for AI workloads
Domain
Semiconductor / Networking / AI Systems
Deliverable
production ML models
Required skills
RTL design (Verilog, SystemVerilog), C/C++ programming, Python/Tcl/Shell scripting, microarchitecture definition, performance/power/area optimization, SoC integration, post-silicon debug
Preferred skills
ARM/RISC-V SoC design, Network-on-Chip (NoC) architecture, AXI/AMBA protocols, P4 programmable packet processing, high-performance interconnect design
Technologies
Verilog, SystemVerilog, C, C++, Python, Tcl, Shell, P4, AXI, AMBA, NoC
Responsibilities
Architect and design key blocks for next-generation DPU ASICs, contribute across the full ASIC development lifecycle, collaborate on advanced network processing engines including P4-based solutions, debug and resolve issues across simulation, emulation, and post-silicon phases, support integration of ASIC IPs into larger SoC architectures
Seniority
Senior, hands-on IC
