Senior RTL Silicon Design & Validation Engineer
Core
Design, plan, and execute RTL design for next-generation PCIe, CXL, and connectivity solutions for programmable silicon.
Role type
Senior RTL Silicon Design & Validation Engineer
Builds
High-speed PCIe Gen6/Gen7, CXL, TDISP, IDE, and PCIe in-line DMA technologies for datacenter, AI, and communications markets.
Domain
Semiconductor / High-speed Interface Protocols
Required skills
RTL coding (Verilog, SystemVerilog), RTL simulation (VCS, ModelSim), IP/SOC design methodologies, high-speed interface protocols (PCIe, CXL, NVMe, Ethernet, DDR, HBM, AMBA), FPGA prototyping, scripting (Tcl, Perl, Python, Unix shells, Makefiles)
Preferred skills
Lab equipment usage (Lecroy/Viavi Exerciser/Analyzer), C/C++ knowledge
Technologies
VCS, ModelSim, Tcl, Perl, Python, Unix shells, Makefiles, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB, FPGA
Responsibilities
Develop and productize next generation PCIe, CXL and connectivity solutions; Participate in technical role in all phases of the product development cycle from architecture through validation and support; Develop comprehensive testing plans including Compliance and Interop testing; Perform Pre-Silicon and Post Silicon validation for new PCIe enabled blocks; Responsible for IP design, Silicon bring up, Validation and IP release
Seniority
Senior, hands-on IC
