Digital Verification Engineer
Core
ASIC Design Verification Engineer for System-on-Chip (SoC) in Neuralink's Implant Team, focusing on high-throughput low-power digital signal processing (DSP) for brain-computer interfaces.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Architecture and logic implementation of digital modules for brain-computer interface SoCs
Domain
Medical devices / Brain-Computer Interfaces / ASIC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Python, Perl, Tcl, UNIX shell, code coverage, regression setup, formal verification, IEEE-1801 (UPF), low power gate level simulation, ARM/RISC-V processor, AMBA bus, FPGA/emulation, lab system bring up, diagnostic writing, lab debugging
Preferred skills
Complex digital systems architecture/microarchitecture/RTL/verification/physical design, test bench building, debugging, functional modeling, SystemC/C++, power aware verification
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, UNIX shell, IEEE-1801, ARM, RISC-V, AMBA, FPGA
Responsibilities
Develop automation flow and scripts for verification; build test benches for complex SoC; perform formal verification; conduct low power gate level simulations; execute lab system bring up and debugging
Seniority
Mid-Senior, hands-on IC
