Layout Verification / PEX Engineer
Core
Physical and electrical verification of photonic integrated circuits within a silicon photonics technology platform for quantum computers.
Role type
IC layout verification engineer (silicon photonics)
Builds
Silicon photonics technology platform for utility-scale quantum computers
Domain
Quantum computing / Silicon photonics / Semiconductor manufacturing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC layout verification, DRC, LVS, ERC, parasitic extraction, Linux/Unix environments, attention to detail
Preferred skills
Analog/mixed-signal IC layout, Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, post-layout simulation flows, Python scripting, silicon photonics
Technologies
Cadence Virtuoso, Siemens Calibre, Cadence Pegasus, Cadence Quantus, Linux, Unix
Responsibilities
Run DRC, LVS, ERC, antenna, density, and parasitic extraction flows; Validate electrical routing in photonic integrated circuit layouts; Generate extracted netlists and views for post-layout simulation; Maintain verification logs and reports; Support block-level and chip-level verification prior to tapeout
Seniority
Mid-level, hands-on IC engineer