NPU Architect Engineer, Multimedia Lab
Core
Design hardware accelerators for advanced video encoding and processing, focusing on NPU modules for next-generation chips.
Role type
Senior IC NPU Architect Engineer
Builds
Video codec hardware solutions (FPGA and ASIC) for large-scale video platforms
Domain
Semiconductor / AI Hardware Acceleration
Deliverable
production ML models
Required skills
Hardware architecture design, Performance modeling, Hardware-software co-optimization, Microarchitecture specification, Deep learning algorithm analysis, Chip specification definition
Preferred skills
Tape-out experience, SoC subsystem architecture knowledge, Hardware Emulation (Palladium, ZeBu), FPGA prototyping, Formal Verification, SoC-level Performance and Power-Aware verification
Technologies
FPGA, ASIC, Tensor Core, Palladium, ZeBu, JasperGold
Responsibilities
Design hardware architecture for NPU modules, Perform performance modeling for deep learning algorithms, Optimize architecture for real-world scenarios, Author architecture specification documents
Seniority
Senior, hands-on IC
